As semiconductor technology advances, a supply voltage required for powering a memory device has become lower. Under a circumstance where a fabrication process of the memory device varies to a worst corner, write operations of the memory device may fail because of an insufficient operation voltage range. In order to solve this problem, negative bit line (NBL) techniques are proposed and widely used in various types of memory devices (including static random access memory (SRAM) devices), so as to increase the operation voltage range during the write operations.
FIG. 1 illustrates a conventional SRAM device that uses the NBL techniques. For convenience of illustration of the conventional SRAM device, one of memory cells (e.g., the memory cell 91), one of non-inverting bit lines (e.g., the non-inverting bit line (BL1)), one of write drivers (e.g., the write driver 92) and one of negative voltage generators (e.g., the negative voltage generator 93) are depicted in FIG. 1 and will be described in detail below, the write driver 92 is represented as an inverter in FIG. 1, and inverting bit lines, non-inverting word lines and inverting word lines are all omitted in FIG. 1 and the following description.
The non-inverting bit line (BL1) is connected to the memory cell 91. The write driver 92 has a power terminal that is for receiving a supply voltage (VCC), a ground terminal, an input terminal that is for receiving a logic signal (D), and an output terminal that is connected to the non-inverting bit line (BL1). The negative voltage generator 93 is connected to the ground terminal of the write driver 92, and generates, for receipt by the ground terminal of the write driver 92, a reference voltage (VG1) that is selectively equal to or lower than a ground voltage.
When logic zero is to be written to the memory cell 91, the logic signal (D) is in a logic one state and has a voltage equal to the supply voltage (VCC) of, for example, 1 Volt, and the reference voltage (VG1) is lower than the around voltage by, for example, several hundred milli-Volts, so a signal at the non-inverting bit line (BL1) is in a logic zero state and has a voltage lower than the ground voltage, thereby increasing an operation voltage range of the conventional SRAM device. However, at this time, a voltage between the input terminal and the ground terminal of the write driver 92 is higher than the supply voltage (VCC), and the write driver 92 may endure overly high stress voltage and may be damaged when this voltage is greater than a designed value (e.g., 1.4 times the supply voltage (VCC)) because of fabrication variations of the conventional SRAM device. In other words, the NBL techniques can increase the operation voltage range to prevent write failures of the conventional SRAM device, but may induce overly high stress voltage endured by each write driver to result in shortened lifetime of the conventional SRAM device.